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Transaction-level modeling
Results: 23

#	Item
11	F R A U N H O F E R I N S T I T U T E F O R I N T E G R AT E D C I R C U I T S I I S D E S I G N A U T O M AT I O N D I V I S I O N E A S © Alexandr Mitiuc - Fotolia.com SERVICES AND DESIGN Add to Reading List Source URL: www.eas.iis.fraunhofer.de Language: English - Date: 2015-01-16 02:39:01 SystemC Transaction-level modeling Esterel Studio Electronic engineering Electronic design automation Hardware description languages
12	Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration Add to Reading List Source URL: www.engr.colostate.edu Language: English - Date: 2004-06-11 02:36:08 Computer buses Transaction-level modeling SystemC Advanced Microcontroller Bus Architecture System on a chip Electronic system-level design and verification CoreConnect High-level synthesis Modeling language Electronic engineering Electronic design automation Digital electronics
13	WILLEMS LAYOUT[removed]:43 AM Add to Reading List Source URL: www.synopsys.com Language: English Logic design Hardware description languages Hardware verification languages Post-silicon validation Prototype FPGA prototype Field-programmable gate array System on a chip Transaction-level modeling Electronic engineering Electronic design automation Electronic design
14	PROJECT RESULT Design methodologies A508: Specification and algorithm/architecture co-design for highly complex applications in automotive and communication (SpeAC) Add to Reading List Source URL: www.catrene.org Language: English - Date: 2009-03-25 10:39:11 Hardware verification languages Electronic system-level design and verification SystemC Transaction-level modeling Systems Modeling Language Systems engineering SIGNAL Integrated circuit design E Electronic engineering Electronic design automation Hardware description languages
15	Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development Napa, Calif., USA, 15 October[removed]Accellera Systems Initiative (A Add to Reading List Source URL: www.ocpip.org Language: English - Date: 2013-10-15 11:21:21 Accellera Hardware verification languages Hardware description languages Open Core Protocol International Partnership Association Open Core Protocol SPIRIT Consortium Transaction-level modeling SystemC IP-XACT Electronic engineering Electronic design automation Standards organizations
16	3855 SW 153rd Drive Beaverton, Oregon[removed]USA Phone: [removed]Fax: [removed]email: [removed] www.ocpip.org Add to Reading List Source URL: www.ocpip.org Language: English - Date: 2011-05-26 14:53:19 Open Core Protocol SystemC Electronic engineering Electronic design automation Transaction-level modeling
17	PINAPA: An Extraction Tool for SystemC Descriptions of Systems-on-a-Chip ∗† Matthieu Moy [removed] Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2005-09-08 19:36:32 Logic design Electronic design automation SystemC Transaction-level modeling NCSim CPU design E Verilog VHDL Electronic engineering Hardware description languages Hardware verification languages
18	System Level Design Using the SystemC Modeling Platform 1 Joachim Gerlach, University of Tübingen, Germany [removed] Add to Reading List Source URL: www.ee.ryerson.ca Language: English - Date: 2004-01-08 11:59:32 Hardware verification languages SystemC Transaction-level modeling Catapult C Electronic engineering Electronic design automation Hardware description languages
19	Comparison of Embedded System Models: From Signals to Transactions Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2010-08-24 10:34:21 Electronic design automation Transaction-level modeling Hard
20	PDF Document Add to Reading List Source URL: www.irisa.fr Language: English - Date: 2010-01-19 06:22:13 SystemC Logic simulation Simulation Full system simulator Transaction-level modeling Catapult C Electronic engineering Digital electronics Electronic design automation